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authorAlexandre TORGUE <alexandre.torgue@st.com>2016-04-01 12:37:30 +0300
committerDavid S. Miller <davem@davemloft.net>2016-04-03 03:23:08 +0300
commit48863ce5940fa5420096c8beba44e5e1bc0c8ca1 (patch)
tree18f4790a802e5b90834586887b819eb2d34e18af /drivers/net/ethernet/toshiba
parent35f74c0c5dce138bd9000d98abf4959af782a96d (diff)
downloadlinux-48863ce5940fa5420096c8beba44e5e1bc0c8ca1.tar.xz
stmmac: add DMA support for GMAC 4.xx
DMA behavior is linked to descriptor management: -descriptor mechanism (Tx for example, but it is exactly the same for RX): -useful registers: -DMA_CH#_TxDesc_Ring_Len: length of transmit descriptor ring -DMA_CH#_TxDesc_List_Address: start address of the ring -DMA_CH#_TxDesc_Tail_Pointer: address of the last descriptor to send + 1. -DMA_CH#_TxDesc_Current_App_TxDesc: address of the current descriptor -The descriptor Tail Pointer register contains the pointer to the descriptor address (N). The base address and the current descriptor decide the address of the current descriptor that the DMA can process. The descriptors up to one location less than the one indicated by the descriptor tail pointer (N-1) are owned by the DMA. The DMA continues to process the descriptors until the following condition occurs: "current descriptor pointer == Descriptor Tail pointer" Then the DMA goes into suspend mode. The application must perform a write to descriptor tail pointer register and update the tail pointer to have the following condition and to start a new transfer: "current descriptor pointer < Descriptor tail pointer" The DMA automatically wraps around the base address when the end of ring is reached. Up to 8 DMA could be use but currently we only use one (channel0) Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/toshiba')
0 files changed, 0 insertions, 0 deletions