diff options
| author | Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2013-03-26 08:43:07 +0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-03-26 20:53:36 +0400 |
| commit | 0982a0f6d1be5f03ba62ed1f3deb92e8376b1e43 (patch) | |
| tree | 12c9d08551c6e6a0efcf4ffd17eeca31ad637d01 /drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | |
| parent | c24602ef86649376e9d71ea808cd877e414d340b (diff) | |
| download | linux-0982a0f6d1be5f03ba62ed1f3deb92e8376b1e43.tar.xz | |
stmmac: start adding pcs and rgmii core irq
This patch starts adding in the main ISR the management of the PCS and
RGMII/SGMII core interrupts. This is to help further development
on this area. Currently the core irq handler only clears the
PCS and S-R_MII interrupts and reports the event in the ethtool stats.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Tested-by: Byungho An <bh74.an@samsung.com>
Cc: Udit Kumar <udit-dlh.kumar@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac1000.h')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h index 85466e5a70b7..6dd689e19f0a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h @@ -89,13 +89,14 @@ enum power_event { (reg * 8)) #define GMAC_MAX_PERFECT_ADDRESSES 32 +/* PCS registers (AN/TBI/SGMII/RGMII) offset */ #define GMAC_AN_CTRL 0x000000c0 /* AN control */ #define GMAC_AN_STATUS 0x000000c4 /* AN status */ #define GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */ -#define GMAC_ANE_LINK 0x000000cc /* Auto-Neg. link partener ability */ +#define GMAC_ANE_LPA 0x000000cc /* Auto-Neg. link partener ability */ #define GMAC_ANE_EXP 0x000000d0 /* ANE expansion */ #define GMAC_TBI 0x000000d4 /* TBI extend status */ -#define GMAC_GMII_STATUS 0x000000d8 /* S/R-GMII status */ +#define GMAC_S_R_GMII 0x000000d8 /* SGMII RGMII status */ /* GMAC Configuration defines */ #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */ |