diff options
| author | Ben Hutchings <bhutchings@solarflare.com> | 2012-02-15 05:58:49 +0400 |
|---|---|---|
| committer | Ben Hutchings <bhutchings@solarflare.com> | 2012-02-16 04:25:12 +0400 |
| commit | 28e47c498a931200125e299e9d60d22e27b4ab0d (patch) | |
| tree | 871e75c4db7e670c2ceaed7b5fd69b9ef9a5f4c4 /drivers/net/ethernet/sfc/siena.c | |
| parent | a9a52506277275b73955504bf4df745502a28b8b (diff) | |
| download | linux-28e47c498a931200125e299e9d60d22e27b4ab0d.tar.xz | |
sfc: Allocate SRAM between buffer table and descriptor caches at init time
Each port has a block of 64-bit SRAM that is divided between buffer
table and descriptor cache regions at initialisation time. Currently
we use a fixed allocation, but it needs to be changed to support
larger numbers of queues.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat (limited to 'drivers/net/ethernet/sfc/siena.c')
| -rw-r--r-- | drivers/net/ethernet/sfc/siena.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/net/ethernet/sfc/siena.c b/drivers/net/ethernet/sfc/siena.c index d3c4169e2a0b..657f3fa93bcf 100644 --- a/drivers/net/ethernet/sfc/siena.c +++ b/drivers/net/ethernet/sfc/siena.c @@ -225,6 +225,15 @@ static int siena_probe_nvconfig(struct efx_nic *efx) return rc; } +static void siena_dimension_resources(struct efx_nic *efx) +{ + /* Each port has a small block of internal SRAM dedicated to + * the buffer table and descriptor caches. In theory we can + * map both blocks to one port, but we don't. + */ + efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2); +} + static int siena_probe_nic(struct efx_nic *efx) { struct siena_nic_data *nic_data; @@ -619,6 +628,7 @@ const struct efx_nic_type siena_a0_nic_type = { .probe = siena_probe_nic, .remove = siena_remove_nic, .init = siena_init_nic, + .dimension_resources = siena_dimension_resources, .fini = efx_port_dummy_op_void, .monitor = NULL, .map_reset_reason = siena_map_reset_reason, @@ -657,8 +667,6 @@ const struct efx_nic_type siena_a0_nic_type = { * interrupt handler only supports 32 * channels */ .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH, - .tx_dc_base = 0x88000, - .rx_dc_base = 0x68000, .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE), }; |