diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-04-01 00:23:51 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-04-01 21:09:53 +0300 |
| commit | e14549a50a6c5e3320bb941440b1c3ae4812ea69 (patch) | |
| tree | 067f91f3dcb5cb4c664304af76c201183cf88df8 /drivers/net/ethernet/renesas/sh_eth.c | |
| parent | 6e80e55bd37a90b412f168b1667ffa7d2debd46b (diff) | |
| download | linux-e14549a50a6c5e3320bb941440b1c3ae4812ea69.tar.xz | |
sh_eth: kill useless check in __sh_eth_get_regs()
Iff TSU registers exist on a given [G]Ether controller, they always include
the CAM entry table registers (TSU_ADR{H|L}<n>), thus the check for invalid
TSU_ADRH0 offset in __sh_eth_get_regs() is useless...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/renesas/sh_eth.c')
| -rw-r--r-- | drivers/net/ethernet/renesas/sh_eth.c | 25 |
1 files changed, 10 insertions, 15 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 2bff03345b72..b6b90a6314e3 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -2153,22 +2153,17 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) add_tsu_reg(TSU_POST2); add_tsu_reg(TSU_POST3); add_tsu_reg(TSU_POST4); - if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { - /* This is the start of a table, not just a single - * register. - */ - if (buf) { - unsigned int i; - - mark_reg_valid(TSU_ADRH0); - for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) - *buf++ = ioread32( - mdp->tsu_addr + - mdp->reg_offset[TSU_ADRH0] + - i * 4); - } - len += SH_ETH_TSU_CAM_ENTRIES * 2; + /* This is the start of a table, not just a single register. */ + if (buf) { + unsigned int i; + + mark_reg_valid(TSU_ADRH0); + for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) + *buf++ = ioread32(mdp->tsu_addr + + mdp->reg_offset[TSU_ADRH0] + + i * 4); } + len += SH_ETH_TSU_CAM_ENTRIES * 2; } #undef mark_reg_valid |