diff options
| author | Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> | 2017-01-27 22:46:26 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-01-30 02:35:43 +0300 |
| commit | 61fccb2d6274f77de6d16a0dc74eda813e90eb64 (patch) | |
| tree | 9c1d205f1f64c2af2296b4956247249ace5fc625 /drivers/net/ethernet/renesas/ravb.h | |
| parent | 1a28242bac44b9eb24fb2e84131256cb3c63372c (diff) | |
| download | linux-61fccb2d6274f77de6d16a0dc74eda813e90eb64.tar.xz | |
ravb: Add tx and rx clock internal delays mode of APSR
This patch enables tx and rx clock internal delay modes (TDM and RDM).
This is to address a failure in the case of 1Gbps communication using the
by salvator-x board with the KSZ9031RNX phy. This has been reported to
occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs.
With this change APSR internal delay modes are enabled for
"rgmii-id", "rgmii-rxid" and "rgmii-txid" phy modes as follows:
phy mode | ASPR delay mode
-----------+----------------
rgmii-id | TDM and RDM
rgmii-rxid | RDM
rgmii-txid | TDM
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/renesas/ravb.h')
| -rw-r--r-- | drivers/net/ethernet/renesas/ravb.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index f1109661a533..0525bd696d5d 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -76,6 +76,7 @@ enum ravb_reg { CDAR20 = 0x0060, CDAR21 = 0x0064, ESR = 0x0088, + APSR = 0x008C, /* R-Car Gen3 only */ RCR = 0x0090, RQC0 = 0x0094, RQC1 = 0x0098, @@ -248,6 +249,15 @@ enum ESR_BIT { ESR_EIL = 0x00001000, }; +/* APSR */ +enum APSR_BIT { + APSR_MEMS = 0x00000002, + APSR_CMSW = 0x00000010, + APSR_DM = 0x00006000, /* Undocumented? */ + APSR_DM_RDM = 0x00002000, + APSR_DM_TDM = 0x00004000, +}; + /* RCR */ enum RCR_BIT { RCR_EFFS = 0x00000001, |