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| author | David S. Miller <davem@davemloft.net> | 2022-09-17 22:13:41 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-09-17 22:13:41 +0300 |
| commit | 44a8535fb87c5503ce01121278ac3058eef701ec (patch) | |
| tree | 20f8b43d78dc13bdc85ac9b8e43a2838f741fdd5 /drivers/net/ethernet/qualcomm/qca_spi.h | |
| parent | 5947b7f794ca5b96fa097d8d73259aaf18878c31 (diff) | |
| parent | 85a5f9638313a1df7e84e9ea66ecd216133215c2 (diff) | |
| download | linux-44a8535fb87c5503ce01121278ac3058eef701ec.tar.xz | |
Merge branch 'octeontx2-cn10k-ptp'
From: Naveen Mamindlapalli <naveenm@marvell.com>
To: <kuba@kernel.org>, <davem@davemloft.net>, <edumazet@google.com>,
<pabeni@redhat.com>, <richardcochran@gmail.com>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<sgoutham@marvell.com>, <hkelam@marvell.com>
Cc: Naveen Mamindlapalli <naveenm@marvell.com>
Subject: [net-next PATCH 0/4] Add PTP support for CN10K silicon
Date: Sat, 10 Sep 2022 13:24:12 +0530 [thread overview]
Message-ID: <20220910075416.22887-1-naveenm@marvell.com> (raw)
This patchset adds PTP support for CN10K silicon, specifically
to workaround few hardware issues and to add 1-step mode.
Patchset overview:
Patch #1 returns correct ptp timestamp in nanoseconds captured
when external timestamp event occurs.
Patch #2 adds 1-step mode support.
Patch #3 implements software workaround to generate PPS output properly.
Patch #4 provides a software workaround for the rollover register default
value, which causes ptp to return the wrong timestamp.
====================
Acked-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qualcomm/qca_spi.h')
0 files changed, 0 insertions, 0 deletions