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authorMichal Kalderon <michal.kalderon@marvell.com>2019-05-26 15:22:20 +0300
committerDavid S. Miller <davem@davemloft.net>2019-05-26 23:04:11 +0300
commit83bf76e3528ace34c28f8033bfa3d2e3ec9861aa (patch)
treeba796fe9b9f773362aa30dca899f35393c308f8f /drivers/net/ethernet/qlogic/qed/qed_cxt.c
parentcecd7582a63168a3e214097bd8b869c02c966f8f (diff)
downloadlinux-83bf76e3528ace34c28f8033bfa3d2e3ec9861aa.tar.xz
qed: Modify api for performing a dmae to another PF
This patch modifies the dmae API to enable performing a dmae operation to another PF. This enables sharing between the llh entries between PFs and thus increasing the amount of filters per PF under certain configurations. The llh entries require using the dmae since the memory is widebus, which requires atomicity in access. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qed/qed_cxt.c')
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_cxt.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.c b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
index e61d1d905415..8e1bdf58b9e7 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_cxt.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
@@ -2351,7 +2351,8 @@ qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
- reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
+ reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
+ NULL);
if (elem_type == QED_ELEM_CXT) {
u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
@@ -2457,7 +2458,7 @@ qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
(u64) (uintptr_t) &ilt_hw_entry,
reg_offset,
sizeof(ilt_hw_entry) / sizeof(u32),
- 0);
+ NULL);
}
qed_ptt_release(p_hwfn, p_ptt);