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authorAtita Shirwaikar <atita.shirwaikar@intel.com>2012-02-18 06:58:58 +0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2012-03-14 11:47:42 +0400
commitd2f5e7f3af777d52ce110ae60e8cb788bc93141c (patch)
treeba26f920fcd8a77aa3a206e957aa9198e0fc3d66 /drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
parent3ed69d7e318ce17c77d91fd09a963cf48ce3a8a9 (diff)
downloadlinux-d2f5e7f3af777d52ce110ae60e8cb788bc93141c.tar.xz
ixgbe: Fix race condition where RX buffer could become corrupted.
There was a race condition in the reset path where the RX buffer could become corrupted during Fdir configuration.This is due to a HW bug.The fix right now is to lock the buffer while we do the fdir configuration.Since we were using similar workaround for another bug, I moved the existing code to a function and reused it.HW team also recommended that IXGBE_MAX_SECRX_POLL value be changed from 30 to 40.The erratum for this bug will be published in the next release 82599 Spec Update Signed-off-by: Atita Shirwaikar <atita.shirwaikar@intel.com> Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe_common.c')
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_common.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index 67ec37b731aa..6117bfd924cc 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -2578,6 +2578,58 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
}
/**
+ * ixgbe_disable_rx_buff_generic - Stops the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Stops the receive data path and waits for the HW to internally
+ * empty the Rx security block.
+ **/
+s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
+{
+#define IXGBE_MAX_SECRX_POLL 40
+ int i;
+ int secrxreg;
+
+ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+ secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
+ for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
+ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
+ if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
+ break;
+ else
+ /* Use interrupt-safe sleep just in case */
+ udelay(10);
+ }
+
+ /* For informational purposes only */
+ if (i >= IXGBE_MAX_SECRX_POLL)
+ hw_dbg(hw, "Rx unit being enabled before security "
+ "path fully disabled. Continuing with init.\n");
+
+ return 0;
+
+}
+
+/**
+ * ixgbe_enable_rx_buff - Enables the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Enables the receive data path
+ **/
+s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
+{
+ int secrxreg;
+
+ secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+ secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
+ IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
+ IXGBE_WRITE_FLUSH(hw);
+
+ return 0;
+}
+
+/**
* ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
* @hw: pointer to hardware structure
* @regval: register value to write to RXCTRL