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authorMark Rustad <mark.d.rustad@intel.com>2015-10-27 23:23:14 +0300
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2015-12-03 13:32:12 +0300
commitefff2e027758fd5cc739d500397f729591f32a94 (patch)
tree9fa970bb5b7da8b49c1f3902858e1a9b418eb7d0 /drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
parenta9763f3cb54c7f1c6a47962c814935654476d09f (diff)
downloadlinux-efff2e027758fd5cc739d500397f729591f32a94.tar.xz
ixgbe: Correct spec violations by waiting after reset
The ixgbe driver was violating the specification in the datasheet by not waiting 1ms before checking for the reset bit clearing. This is called out for devices supported by ixgbe, so implement the required delay. Reported-by: Dan Streetman <dan.streetman@canonical.com> Signed-off-by: Mark Rustad <mark.d.rustad@intel.com> Tested-by: Darin Miller <darin.j.miller@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c')
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
index a39afcf03e2c..b8bd72589f72 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
@@ -990,13 +990,14 @@ mac_reset_top:
ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw);
+ usleep_range(1000, 1200);
/* Poll for reset bit to self-clear indicating reset is complete */
for (i = 0; i < 10; i++) {
- udelay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
if (!(ctrl & IXGBE_CTRL_RST_MASK))
break;
+ udelay(1);
}
if (ctrl & IXGBE_CTRL_RST_MASK) {