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authorYunsheng Lin <linyunsheng@huawei.com>2018-11-19 16:02:15 +0300
committerDavid S. Miller <davem@davemloft.net>2018-11-20 05:32:11 +0300
commite432abfb99e5642a7e7fcaa1c8cb0e80c8fcf58e (patch)
tree2442fdccf6556d4979071b27815df239ea147b62 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
parent43478201959da54d8e3058f9a017111749c6ace6 (diff)
downloadlinux-e432abfb99e5642a7e7fcaa1c8cb0e80c8fcf58e.tar.xz
net: hns3: add common validation in hclge_dcb
Before setting tm related configuration to hardware, driver needs to check the configuration provided by user is valid. Currently hclge_ieee_setets and hclge_setup_tc both implement their own checking, which has a lot in common. This patch addes hclge_dcb_common_validate to do the common checking. The checking in hclge_tm_prio_tc_info_update and hclge_tm_schd_info_update is unnecessary now, so change the return type to void, which removes the need to do error handling when one of the checking fails. Also, ets->prio_tc is indexed by user prio and ets->tc_tsa is indexed by tc num, so this patch changes them to use different index. Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com> Signed-off-by: Tan Xiaojun <tanxiaojun@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h')
-rw-r--r--drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
index 25eef13a3e14..4bd916a77ae2 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
@@ -131,8 +131,8 @@ struct hclge_port_shapping_cmd {
int hclge_tm_schd_init(struct hclge_dev *hdev);
int hclge_pause_setup_hw(struct hclge_dev *hdev);
int hclge_tm_schd_mode_hw(struct hclge_dev *hdev);
-int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
-int hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
+void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
+void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
int hclge_tm_map_cfg(struct hclge_dev *hdev);
int hclge_tm_init_hw(struct hclge_dev *hdev);