diff options
| author | Doug Berger <opendmb@gmail.com> | 2020-05-01 02:26:51 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-05-02 01:54:33 +0300 |
| commit | eb236c2994b031f805be691fa9ea39cba4690166 (patch) | |
| tree | ccfec9cd9cf2e3835252bc4901c4b02a90faa326 /drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c | |
| parent | df8f348e76d556cc88445fd78e83235a910cb41e (diff) | |
| download | linux-eb236c2994b031f805be691fa9ea39cba4690166.tar.xz | |
net: bcmgenet: Move wake-up event out of side band ISR
The side band interrupt service routine is not available on chips
like 7211, or rather, it does not permit the signaling of wake-up
events due to the complex interrupt hierarchy.
Move the wake-up event accounting into a .resume_noirq function,
account for possible wake-up events and clear the MPD/HFB interrupts
from there, while leaving the hardware untouched until the resume
function proceeds with doing its usual business.
Because bcmgenet_wol_power_down_cfg() now enables the MPD and HFB
interrupts, it is invoked by a .suspend_noirq function to prevent
the servicing of interrupts after the clocks have been disabled.
Signed-off-by: Doug Berger <opendmb@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c')
| -rw-r--r-- | drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c index 4b9d65f392c2..4ea6a26b04f7 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c @@ -193,6 +193,12 @@ int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); } + reg = UMAC_IRQ_MPD_R; + if (hfb_enable) + reg |= UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM; + + bcmgenet_intrl2_0_writel(priv, reg, INTRL2_CPU_MASK_CLEAR); + return 0; } |