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authorAlexandru Tachici <alexandru.tachici@analog.com>2022-09-13 15:26:28 +0300
committerPaolo Abeni <pabeni@redhat.com>2022-09-20 16:00:30 +0300
commitbc93e19d088bb14e116756ab270deea6ee62d782 (patch)
tree0464ee96fe95302dfdf358aa4962d378bcd57223 /drivers/net/ethernet/adi/Makefile
parent875b718ac380eeb84e452be6a83cdbb8452a2bcb (diff)
downloadlinux-bc93e19d088bb14e116756ab270deea6ee62d782.tar.xz
net: ethernet: adi: Add ADIN1110 support
The ADIN1110 is a low power single port 10BASE-T1L MAC-PHY designed for industrial Ethernet applications. It integrates an Ethernet PHY core with a MAC and all the associated analog circuitry, input and output clock buffering. ADIN1110 MAC-PHY encapsulates the ADIN1100 PHY. The PHY registers can be accessed through the MDIO MAC registers. We are registering an MDIO bus with custom read/write in order to let the PHY to be discovered by the PAL. This will let the ADIN1100 Linux driver to probe and take control of the PHY. The ADIN2111 is a low power, low complexity, two-Ethernet ports switch with integrated 10BASE-T1L PHYs and one serial peripheral interface (SPI) port. The device is designed for industrial Ethernet applications using low power constrained nodes and is compliant with the IEEE 802.3cg-2019 Ethernet standard for long reach 10 Mbps single pair Ethernet (SPE). The switch supports various routing configurations between the two Ethernet ports and the SPI host port providing a flexible solution for line, daisy-chain, or ring network topologies. The ADIN2111 supports cable reach of up to 1700 meters with ultra low power consumption of 77 mW. The two PHY cores support the 1.0 V p-p operating mode and the 2.4 V p-p operating mode defined in the IEEE 802.3cg standard. The device integrates the switch, two Ethernet physical layer (PHY) cores with a media access control (MAC) interface and all the associated analog circuitry, and input and output clock buffering. The device also includes internal buffer queues, the SPI and subsystem registers, as well as the control logic to manage the reset and clock control and hardware pin configuration. Access to the PHYs is exposed via an internal MDIO bus. Writes/reads can be performed by reading/writing to the ADIN2111 MDIO registers via SPI. On probe, for each port, a struct net_device is allocated and registered. When both ports are added to the same bridge, the driver will enable offloading of frame forwarding at the hardware level. Driver offers STP support. Normal operation on forwarding state. Allows only frames with the 802.1d DA to be passed to the host when in any of the other states. When both ports of ADIN2111 belong to the same SW bridge a maximum of 12 FDB entries will offloaded by the hardware and are marked as such. Co-developed-by: Lennart Franzen <lennart@lfdomain.com> Signed-off-by: Lennart Franzen <lennart@lfdomain.com> Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'drivers/net/ethernet/adi/Makefile')
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1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/adi/Makefile b/drivers/net/ethernet/adi/Makefile
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+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+#
+# Makefile for the Analog Devices network device drivers.
+#
+
+obj-$(CONFIG_ADIN1110) += adin1110.o