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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-08-09 10:03:47 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-08-09 10:03:47 +0300
commitbd935a7b21340e2e37f51a7f2d3188145e2fcf1f (patch)
treeac8af4e6ea552d32839c415b2f36d416ee327ea4 /drivers/net/dsa/qca/ar9331.c
parent96ba6c6e8922e89ca4908c650072d8f8d7b39cbc (diff)
parent36a21d51725af2ce0700c6ebcb6b9594aac658a6 (diff)
downloadlinux-bd935a7b21340e2e37f51a7f2d3188145e2fcf1f.tar.xz
Merge 5.14-rc5 into driver-core-next
We need the driver core fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/net/dsa/qca/ar9331.c')
-rw-r--r--drivers/net/dsa/qca/ar9331.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c
index ca2ad77b71f1..6686192e1883 100644
--- a/drivers/net/dsa/qca/ar9331.c
+++ b/drivers/net/dsa/qca/ar9331.c
@@ -837,16 +837,24 @@ static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
return 0;
}
- ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
+ /* In case of this switch we work with 32bit registers on top of 16bit
+ * bus. Some registers (for example access to forwarding database) have
+ * trigger bit on the first 16bit half of request, the result and
+ * configuration of request in the second half.
+ * To make it work properly, we should do the second part of transfer
+ * before the first one is done.
+ */
+ ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
+ val >> 16);
if (ret < 0)
goto error;
- ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
- val >> 16);
+ ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
if (ret < 0)
goto error;
return 0;
+
error:
dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
return ret;