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authorVladimir Oltean <vladimir.oltean@nxp.com>2020-07-05 19:16:24 +0300
committerDavid S. Miller <davem@davemloft.net>2020-07-06 01:25:58 +0300
commit151a7cee728a89d909096f552108692905b66aaa (patch)
tree640d04cb81b5a6f9984c94cb71d1aaf926018df1 /drivers/net/dsa/ocelot
parentda1c4ba1f741ee8f7a7f88d52bc2482fae26200d (diff)
downloadlinux-151a7cee728a89d909096f552108692905b66aaa.tar.xz
net: dsa: felix: set proper pause frame timers based on link speed
state->speed holds a value of 10, 100, 1000 or 2500, but SYS_MAC_FC_CFG_FC_LINK_SPEED expects a value in the range 0, 1, 2 or 3. So set the correct speed encoding into this register. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/ocelot')
-rw-r--r--drivers/net/dsa/ocelot/felix.c27
1 files changed, 23 insertions, 4 deletions
diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c
index 4d819cc45bed..4684339012c5 100644
--- a/drivers/net/dsa/ocelot/felix.c
+++ b/drivers/net/dsa/ocelot/felix.c
@@ -250,10 +250,25 @@ static void felix_phylink_mac_config(struct dsa_switch *ds, int port,
DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
DEV_CLOCK_CFG);
- /* Flow control. Link speed is only used here to evaluate the time
- * specification in incoming pause frames.
- */
- mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(state->speed);
+ switch (state->speed) {
+ case SPEED_10:
+ mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3);
+ break;
+ case SPEED_100:
+ mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2);
+ break;
+ case SPEED_1000:
+ case SPEED_2500:
+ mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1);
+ break;
+ case SPEED_UNKNOWN:
+ mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(0);
+ break;
+ default:
+ dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
+ port, state->speed);
+ return;
+ }
/* handle Rx pause in all cases, with 2500base-X this is used for rate
* adaptation.
@@ -265,6 +280,10 @@ static void felix_phylink_mac_config(struct dsa_switch *ds, int port,
SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
+
+ /* Flow control. Link speed is only used here to evaluate the time
+ * specification in incoming pause frames.
+ */
ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);