diff options
| author | Vivien Didelot <vivien.didelot@savoirfairelinux.com> | 2017-06-15 19:14:03 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-06-15 21:07:49 +0300 |
| commit | d77f4321fa5cbe393930855763adaa87046394c6 (patch) | |
| tree | be9e7453a6b0a44baa6b5858977c1c1a0ad15f4e /drivers/net/dsa/mv88e6xxx/global1.c | |
| parent | 7ec60d6e2c400700c740849c9c980aa46499aab4 (diff) | |
| download | linux-d77f4321fa5cbe393930855763adaa87046394c6.tar.xz | |
net: dsa: mv88e6xxx: prefix Global Control macros
Prefix and document the Global Control and Control 2 registers macros
and give a clear 16-bit registers representation.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/mv88e6xxx/global1.c')
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx/global1.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c index 0ddf1021442b..63e3ad1ba52a 100644 --- a/drivers/net/dsa/mv88e6xxx/global1.c +++ b/drivers/net/dsa/mv88e6xxx/global1.c @@ -162,14 +162,14 @@ int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart * the PPU, including re-doing PHY detection and initialization */ - err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); + err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); if (err) return err; - val |= GLOBAL_CONTROL_SW_RESET; - val |= GLOBAL_CONTROL_PPU_ENABLE; + val |= MV88E6XXX_G1_CTL1_SW_RESET; + val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; - err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val); + err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); if (err) return err; @@ -186,13 +186,13 @@ int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) int err; /* Set the SWReset bit 15 */ - err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); + err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); if (err) return err; - val |= GLOBAL_CONTROL_SW_RESET; + val |= MV88E6XXX_G1_CTL1_SW_RESET; - err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val); + err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); if (err) return err; @@ -208,13 +208,13 @@ int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) u16 val; int err; - err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); + err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); if (err) return err; - val |= GLOBAL_CONTROL_PPU_ENABLE; + val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; - err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val); + err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); if (err) return err; @@ -226,13 +226,13 @@ int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) u16 val; int err; - err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); + err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); if (err) return err; - val &= ~GLOBAL_CONTROL_PPU_ENABLE; + val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; - err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val); + err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); if (err) return err; @@ -342,13 +342,13 @@ int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) u16 val; int err; - err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL_2, &val); + err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &val); if (err) return err; - val |= GLOBAL_CONTROL_2_HIST_RX_TX; + val |= MV88E6XXX_G1_CTL2_HIST_RX_TX; - err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, val); + err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, val); return err; } |