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authorJeff Garzik <jeff@garzik.org>2006-09-13 21:24:59 +0400
committerJeff Garzik <jeff@garzik.org>2006-09-13 21:24:59 +0400
commit6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch)
treedf0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/au1000_eth.h
parent7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff)
downloadlinux-6aa20a2235535605db6d6d2bd850298b2fe7f31e.tar.xz
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/au1000_eth.h')
-rw-r--r--drivers/net/au1000_eth.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/au1000_eth.h b/drivers/net/au1000_eth.h
index 41c2f848d2c4..52fe00dd6d24 100644
--- a/drivers/net/au1000_eth.h
+++ b/drivers/net/au1000_eth.h
@@ -23,7 +23,7 @@
*
* ########################################################################
*
- *
+ *
*/
@@ -40,8 +40,8 @@
#define MULTICAST_FILTER_LIMIT 64
-/*
- * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
+/*
+ * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
* boundary for both, receive and transmit.
*/
typedef struct db_dest {
@@ -51,7 +51,7 @@ typedef struct db_dest {
} db_dest_t;
/*
- * The transmit and receive descriptors are memory
+ * The transmit and receive descriptors are memory
* mapped registers.
*/
typedef struct tx_dma {
@@ -107,9 +107,9 @@ struct au1000_private {
struct phy_device *phy_dev;
struct mii_bus mii_bus;
-
+
/* These variables are just for quick access to certain regs addresses. */
- volatile mac_reg_t *mac; /* mac registers */
+ volatile mac_reg_t *mac; /* mac registers */
volatile u32 *enable; /* address of MAC Enable Register */
u32 vaddr; /* virtual address of rx/tx buffers */