summaryrefslogtreecommitdiff
path: root/drivers/mtd/nand/raw/nandsim.c
diff options
context:
space:
mode:
authorJakub Kicinski <kuba@kernel.org>2023-03-31 00:43:03 +0300
committerJakub Kicinski <kuba@kernel.org>2023-03-31 00:43:03 +0300
commit79548b7984e4c606c6caaad72a0864a83855ebc9 (patch)
tree05e1be823acbae8bbcd155a706eb9e4f84eee047 /drivers/mtd/nand/raw/nandsim.c
parentda617cd8d90608582eb8d0b58026f31f1a9bfb1d (diff)
parentb2bc47e9b2011a183f9d3d3454a294a938082fb9 (diff)
downloadlinux-79548b7984e4c606c6caaad72a0864a83855ebc9.tar.xz
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Conflicts: drivers/net/ethernet/mediatek/mtk_ppe.c 3fbe4d8c0e53 ("net: ethernet: mtk_eth_soc: ppe: add support for flow accounting") 924531326e2d ("net: ethernet: mtk_eth_soc: add missing ppe cache flush when deleting a flow") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/mtd/nand/raw/nandsim.c')
-rw-r--r--drivers/mtd/nand/raw/nandsim.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/mtd/nand/raw/nandsim.c b/drivers/mtd/nand/raw/nandsim.c
index c21abf748948..179b28459b4b 100644
--- a/drivers/mtd/nand/raw/nandsim.c
+++ b/drivers/mtd/nand/raw/nandsim.c
@@ -2160,8 +2160,23 @@ static int ns_exec_op(struct nand_chip *chip, const struct nand_operation *op,
const struct nand_op_instr *instr = NULL;
struct nandsim *ns = nand_get_controller_data(chip);
- if (check_only)
+ if (check_only) {
+ /* The current implementation of nandsim needs to know the
+ * ongoing operation when performing the address cycles. This
+ * means it cannot make the difference between a regular read
+ * and a continuous read. Hence, this hack to manually refuse
+ * supporting sequential cached operations.
+ */
+ for (op_id = 0; op_id < op->ninstrs; op_id++) {
+ instr = &op->instrs[op_id];
+ if (instr->type == NAND_OP_CMD_INSTR &&
+ (instr->ctx.cmd.opcode == NAND_CMD_READCACHEEND ||
+ instr->ctx.cmd.opcode == NAND_CMD_READCACHESEQ))
+ return -EOPNOTSUPP;
+ }
+
return 0;
+ }
ns->lines.ce = 1;