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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2018-08-22 21:28:01 +0300
committerUlf Hansson <ulf.hansson@linaro.org>2018-08-23 10:58:12 +0300
commit9faf870e559a710c44e747ba20383ea82d8ac5d2 (patch)
tree530c032c8d4ad6dcbe18f925d16bcc0260a36daf /drivers/mmc
parent26caddf274cf1e89fd4ce44ab2b8dbc7a7f97681 (diff)
downloadlinux-9faf870e559a710c44e747ba20383ea82d8ac5d2.tar.xz
mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/renesas_sdhi_internal_dmac.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 35cc0de6be67..f16677f424b9 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -45,7 +45,7 @@
/* DM_CM_RST */
#define RST_DTRANRST1 BIT(9)
#define RST_DTRANRST0 BIT(8)
-#define RST_RESERVED_BITS GENMASK_ULL(32, 0)
+#define RST_RESERVED_BITS GENMASK_ULL(31, 0)
/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
#define INFO1_CLEAR 0