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authorShawn Guo <shawn.guo@linaro.org>2021-03-26 14:02:14 +0300
committerUlf Hansson <ulf.hansson@linaro.org>2021-03-30 13:42:54 +0300
commit25e8b9eb096d057bd5c8095d6a95c16091331e82 (patch)
treead949d4e30be0f1a399f84f6fe60274a9922a986 /drivers/mmc/host
parentf0bdf98fab058efe7bf49732f70a0f26d1143154 (diff)
downloadlinux-25e8b9eb096d057bd5c8095d6a95c16091331e82.tar.xz
mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
As indicated by function esdhc_change_pinstate(), SDR50 and DDR50 require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some system design may support SDR50 and DDR50 with 100mhz pin state only (without 200mhz one). Currently the combined 100/200 MHz pinctrl state check prevents such system from running SDR50 and DDR50. Separate the check to support such system design. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Link: https://lore.kernel.org/r/20210326110214.28416-1-shawnguo@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index d309cc620fdc..a380244db521 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
* Do not advertise faster UHS modes if there are no
* pinctrl states for 100MHz/200MHz.
*/
- if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
- IS_ERR_OR_NULL(imx_data->pins_200mhz))
- val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
- | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
+ if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
+ val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+ if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
+ val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
}
}