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authoryangbo lu <yangbo.lu@nxp.com>2017-04-20 11:14:42 +0300
committerUlf Hansson <ulf.hansson@linaro.org>2017-04-24 22:42:26 +0300
commitba49cbd0936e12eac245c0fb420a291e8505f639 (patch)
treea31cacf823725a4229374e6e73ca7a42e5bce441 /drivers/mmc/host/sdhci-esdhc.h
parentea35645a3c66a74af92d3bbb4eb131220fc3e58a (diff)
downloadlinux-ba49cbd0936e12eac245c0fb420a291e8505f639.tar.xz
mmc: sdhci-of-esdhc: add tuning support
eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-esdhc.h')
-rw-r--r--drivers/mmc/host/sdhci-esdhc.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
index 68695679fed5..c4bbd7485987 100644
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -53,9 +53,14 @@
#define ESDHC_CLOCK_HCKEN 0x00000002
#define ESDHC_CLOCK_IPGEN 0x00000001
+/* Tuning Block Control Register */
+#define ESDHC_TBCTL 0x120
+#define ESDHC_TB_EN 0x00000004
+
/* Control Register for DMA transfer */
#define ESDHC_DMA_SYSCTL 0x40c
#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
+#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
#define ESDHC_DMA_SNOOP 0x00000040
#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */