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| author | Dinh Nguyen <dinguyen@altera.com> | 2014-04-17 00:05:15 +0400 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@altera.com> | 2014-05-06 07:33:18 +0400 |
| commit | 8cb289ed60668d3350dda5aa19b4fa1dce1c07f1 (patch) | |
| tree | 2c254d8089be3b05be5db6db16f07d23ab11986d /drivers/misc/mei/hw-me-regs.h | |
| parent | 16fb4f8bd59e0e954991f624bcc53dad2052ef0d (diff) | |
| download | linux-8cb289ed60668d3350dda5aa19b4fa1dce1c07f1.tar.xz | |
ARM: socfpga: dts: Add div-reg to the main_pll clocks
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.
Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Diffstat (limited to 'drivers/misc/mei/hw-me-regs.h')
0 files changed, 0 insertions, 0 deletions