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| author | Dmitry Osipenko <digetx@gmail.com> | 2019-12-20 05:08:48 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-01-10 17:48:40 +0300 |
| commit | 0f8bb9da5aee80d8d1b716e0fc5441575ff0ef21 (patch) | |
| tree | e1ff65af2cf378509954a05b2bebd15fa2557fdf /drivers/memory/pl172.c | |
| parent | 51bb73f93410a30550641f69d14cfb7b43fd2da1 (diff) | |
| download | linux-0f8bb9da5aee80d8d1b716e0fc5441575ff0ef21.tar.xz | |
memory: tegra30-emc: Firm up hardware programming sequence
Previously there was a problem where a late handshake handling caused
a memory corruption, this problem was resolved by issuing calibration
command right after changing the timing, but looks like the solution
wasn't entirely correct since calibration interval could be disabled as
well. Now programming sequence is completed immediately after receiving
handshake from CaR, without potentially long delays and in accordance to
the TRM's programming guide.
Secondly, the TRM's programming guide suggests to flush EMC writes by
reading any *MC* register before doing CaR changes. This is also addressed
now.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/pl172.c')
0 files changed, 0 insertions, 0 deletions