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authorAl Viro <viro@zeniv.linux.org.uk>2014-06-12 08:27:11 +0400
committerAl Viro <viro@zeniv.linux.org.uk>2014-06-12 08:28:09 +0400
commit9c1d5284c79fea050f115eadeec1dd1758e5c630 (patch)
tree4d16fd5aad7ff4931e985c0128c5747f23561f8a /drivers/memory/mvebu-devbus.c
parent5f073850602084fbcbb987948ff3e70ae273f7d2 (diff)
parent9f12600fe425bc28f0ccba034a77783c09c15af4 (diff)
downloadlinux-9c1d5284c79fea050f115eadeec1dd1758e5c630.tar.xz
Merge commit '9f12600fe425bc28f0ccba034a77783c09c15af4' into for-linus
Backmerge of dcache.c changes from mainline. It's that, or complete rebase... Conflicts: fs/splice.c Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Diffstat (limited to 'drivers/memory/mvebu-devbus.c')
-rw-r--r--drivers/memory/mvebu-devbus.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 110c03627051..b59a17fb7c3e 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -108,8 +108,19 @@ static int devbus_set_timing_params(struct devbus *devbus,
node->full_name);
return err;
}
- /* Convert bit width to byte width */
- r.bus_width /= 8;
+
+ /*
+ * The bus width is encoded into the register as 0 for 8 bits,
+ * and 1 for 16 bits, so we do the necessary conversion here.
+ */
+ if (r.bus_width == 8)
+ r.bus_width = 0;
+ else if (r.bus_width == 16)
+ r.bus_width = 1;
+ else {
+ dev_err(devbus->dev, "invalid bus width %d\n", r.bus_width);
+ return -EINVAL;
+ }
err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
&r.badr_skew);