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| author | Jiri Kosina <jkosina@suse.cz> | 2014-06-04 15:09:01 +0400 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2014-06-04 15:09:01 +0400 |
| commit | af5666e0f76023d9c296016024297903a4c83108 (patch) | |
| tree | 9397e7a41dd3eb0c0e14a6407a8e8f12abed4fc5 /drivers/media/i2c/ths8200.c | |
| parent | 1b15d2e5b8077670b1e6a33250a0d9577efff4a5 (diff) | |
| parent | 368c96640d10a145da5f258f2d2833668d4f3629 (diff) | |
| download | linux-af5666e0f76023d9c296016024297903a4c83108.tar.xz | |
Merge branches 'for-3.15/upstream-fixes' and 'for-3.16/upstream' into for-linus
Conflicts:
drivers/hid/hid-sensor-hub.c
Diffstat (limited to 'drivers/media/i2c/ths8200.c')
| -rw-r--r-- | drivers/media/i2c/ths8200.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/media/i2c/ths8200.c b/drivers/media/i2c/ths8200.c index 04139eec8c4e..f72561e79739 100644 --- a/drivers/media/i2c/ths8200.c +++ b/drivers/media/i2c/ths8200.c @@ -217,8 +217,8 @@ static void ths8200_core_init(struct v4l2_subdev *sd) /* Disable embedded syncs on the output by setting * the amplitude to zero for all channels. */ - ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a); - ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a); + ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00); + ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00); } static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) @@ -318,15 +318,15 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) (htotal(bt) >> 8) & 0x1f); ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); - /* v sync width transmitted */ - ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); + /* v sync width transmitted (must add 1 to get correct output) */ + ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff); ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, - ((bt->vsync) >> 2) & 0xc0); + ((bt->vsync + 1) >> 2) & 0xc0); - /* The pixel value v sync is asserted on */ + /* The pixel value v sync is asserted on (must add 1 to get correct output) */ ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, - (vtotal(bt)>>8) & 0x7); - ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); + ((vtotal(bt) + 1) >> 8) & 0x7); + ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1); /* For progressive video vlength2 must be set to all 0 and vdly2 must * be set to all 1. @@ -336,11 +336,11 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); /* Internal delay factors to synchronize the sync pulses and the data */ - /* Experimental values delays (hor 4, ver 1) */ - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); - ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); + /* Experimental values delays (hor 0, ver 0) */ + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0); + ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0); ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); - ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); + ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0); /* Polarity of received and transmitted sync signals */ if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { @@ -356,7 +356,7 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) /* Timing of video input bus is derived from HS, VS, and FID dedicated * inputs */ - ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity); + ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity); /* leave reset */ ths8200_s_stream(sd, true); |