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| author | Hans Verkuil <hverkuil-cisco@xs4all.nl> | 2018-11-08 12:51:51 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-02-12 21:47:02 +0300 |
| commit | b945ddacf4abd71bad6826ec9f6e0c7f08cd7407 (patch) | |
| tree | bf9bb001919b19be62882bdfbdf4e5ae88af5f23 /drivers/media/i2c/ths8200.c | |
| parent | 9c0403537ecec422aed62181f83837ba5a8ed730 (diff) | |
| download | linux-b945ddacf4abd71bad6826ec9f6e0c7f08cd7407.tar.xz | |
media: adv*/tc358743/ths8200: fill in min width/height/pixelclock
[ Upstream commit 2912289a518077ddb8214e05336700148e97e235 ]
The v4l2_dv_timings_cap struct is used to do sanity checks when setting and
enumerating DV timings, ensuring that only valid timings as per the HW
capabilities are allowed.
However, many drivers just filled in 0 for the minimum width, height or
pixelclock frequency. This can cause timings with e.g. 0 as width and height
to be accepted, which will in turn lead to a potential division by zero.
Fill in proper values are minimum boundaries. 640x350 was chosen since it is
the smallest resolution in v4l2-dv-timings.h. Same for 13 MHz as the lowest
pixelclock frequency (it's slightly below the minimum of 13.5 MHz in the
v4l2-dv-timings.h header).
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ths8200.c')
| -rw-r--r-- | drivers/media/i2c/ths8200.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/media/i2c/ths8200.c b/drivers/media/i2c/ths8200.c index 498ad2368cbc..f5ee28058ea2 100644 --- a/drivers/media/i2c/ths8200.c +++ b/drivers/media/i2c/ths8200.c @@ -49,7 +49,7 @@ static const struct v4l2_dv_timings_cap ths8200_timings_cap = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1080, 25000000, 148500000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1080, 25000000, 148500000, V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE) }; |