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authorLinus Walleij <linus.walleij@linaro.org>2015-12-21 11:36:21 +0300
committerLinus Walleij <linus.walleij@linaro.org>2015-12-21 11:36:21 +0300
commit0529357f102b96f68bc199f858d1c3b07f4b674c (patch)
treeeaa047952a768099e00a5245afa0d84799df6990 /drivers/irqchip/irq-gic-common.c
parenta9f1a3e4c1c7dc82711bc22dc52c7b0d6912ed56 (diff)
parent4ef7675344d687a0ef5b0d7c0cee12da005870c0 (diff)
downloadlinux-0529357f102b96f68bc199f858d1c3b07f4b674c.tar.xz
Merge tag 'v4.4-rc6' into devel
Linux 4.4-rc6
Diffstat (limited to 'drivers/irqchip/irq-gic-common.c')
-rw-r--r--drivers/irqchip/irq-gic-common.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c
index 44a077f3a4a2..f174ce0ca361 100644
--- a/drivers/irqchip/irq-gic-common.c
+++ b/drivers/irqchip/irq-gic-common.c
@@ -84,12 +84,15 @@ void __init gic_dist_config(void __iomem *base, int gic_irqs,
writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
/*
- * Disable all interrupts. Leave the PPI and SGIs alone
- * as they are enabled by redistributor registers.
+ * Deactivate and disable all SPIs. Leave the PPI and SGIs
+ * alone as they are in the redistributor registers on GICv3.
*/
- for (i = 32; i < gic_irqs; i += 32)
+ for (i = 32; i < gic_irqs; i += 32) {
writel_relaxed(GICD_INT_EN_CLR_X32,
- base + GIC_DIST_ENABLE_CLEAR + i / 8);
+ base + GIC_DIST_ACTIVE_CLEAR + i / 8);
+ writel_relaxed(GICD_INT_EN_CLR_X32,
+ base + GIC_DIST_ENABLE_CLEAR + i / 8);
+ }
if (sync_access)
sync_access();
@@ -102,7 +105,9 @@ void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
+ * Make sure everything is deactivated.
*/
+ writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);