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authorMarc Zyngier <maz@kernel.org>2020-03-13 14:01:15 +0300
committerMarc Zyngier <maz@kernel.org>2020-03-16 18:48:54 +0300
commitd5df9dc96eb7423d3f742b13d5e1e479ff795eaa (patch)
tree61c303ae9fcb185194620b60f1354725c0649950 /drivers/irqchip/irq-atmel-aic.c
parentbd59b343a9c902c522f006e6d71080f4893bbf42 (diff)
downloadlinux-d5df9dc96eb7423d3f742b13d5e1e479ff795eaa.tar.xz
irqchip/gic-v3-its: Probe ITS page size for all GITS_BASERn registers
The GICv3 ITS driver assumes that once it has latched on a page size for a given BASER register, it can use the same page size as the maximum page size for all subsequent BASER registers. Although it worked so far, nothing in the architecture guarantees this, and Nianyao Tang hit this problem on some undisclosed implementation. Let's bite the bullet and probe the the supported page size on all BASER registers before starting to populate the tables. This simplifies the setup a bit, at the expense of a few additional MMIO accesses. Signed-off-by: Marc Zyngier <maz@kernel.org> Reported-by: Nianyao Tang <tangnianyao@huawei.com> Tested-by: Nianyao Tang <tangnianyao@huawei.com> Link: https://lore.kernel.org/r/1584089195-63897-1-git-send-email-zhangshaokun@hisilicon.com
Diffstat (limited to 'drivers/irqchip/irq-atmel-aic.c')
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