diff options
| author | CQ Tang <cq.tang@intel.com> | 2016-01-14 00:15:03 +0300 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2016-01-14 02:30:49 +0300 |
| commit | fda3bec12d0979aae3f02ee645913d66fbc8a26e (patch) | |
| tree | 6f90194cfdc2b3fe1e7b84ac488785305a1caa27 /drivers/iommu/dmar.c | |
| parent | e57e58bd390a6843db58560bf7b8341665d2e058 (diff) | |
| download | linux-fda3bec12d0979aae3f02ee645913d66fbc8a26e.tar.xz | |
iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG
This is a 32-bit register. Apparently harmless on real hardware, but
causing justified warnings in simulation.
Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/iommu/dmar.c')
| -rw-r--r-- | drivers/iommu/dmar.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index 80e3c176008e..55a19e49205b 100644 --- a/drivers/iommu/dmar.c +++ b/drivers/iommu/dmar.c @@ -1347,7 +1347,7 @@ void dmar_disable_qi(struct intel_iommu *iommu) raw_spin_lock_irqsave(&iommu->register_lock, flags); - sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); + sts = readl(iommu->reg + DMAR_GSTS_REG); if (!(sts & DMA_GSTS_QIES)) goto end; |