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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-05-08 20:56:45 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-06-14 13:53:17 +0300 |
| commit | 8ff2eb625c353b1491d9f89f1dfd52e7aef5734c (patch) | |
| tree | 423e41ac8e3293d447045d051affe94f06082eb5 /drivers/iio/frequency/ad9523.c | |
| parent | b9ac08b3282a95fcefb057c2886028a6807725d8 (diff) | |
| download | linux-8ff2eb625c353b1491d9f89f1dfd52e7aef5734c.tar.xz | |
iio: frequency: ad9523: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Updated help text to 'may' require buffers to be in their own cacheline.
Fixes: cd1678f96329 ("iio: frequency: New driver for AD9523 SPI Low Jitter Clock Generator")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-66-jic23@kernel.org
Diffstat (limited to 'drivers/iio/frequency/ad9523.c')
| -rw-r--r-- | drivers/iio/frequency/ad9523.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/iio/frequency/ad9523.c b/drivers/iio/frequency/ad9523.c index 942870539268..97662ca1ca96 100644 --- a/drivers/iio/frequency/ad9523.c +++ b/drivers/iio/frequency/ad9523.c @@ -287,13 +287,13 @@ struct ad9523_state { struct mutex lock; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require that + * transfer buffers live in their own cache lines. */ union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr) |