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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 20:56:13 +0300
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 13:53:14 +0300
commit3a828f204a110dc9f253c4cf3c1103d00a0681da (patch)
tree2b7c31c49afab707a5ff81cfea41cec0e4965558 /drivers/iio/adc/ti-adc161s626.c
parent23c81e7a7e5204a08b553d07362d3082926663b8 (diff)
downloadlinux-3a828f204a110dc9f253c4cf3c1103d00a0681da.tar.xz
iio: adc: ti-adc161s626: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 4d671b71beef ("iio: adc: ti-adc161s626: add support for TI 1-channel differential ADCs") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Matt Ranostay <mranostay@gmail.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-34-jic23@kernel.org
Diffstat (limited to 'drivers/iio/adc/ti-adc161s626.c')
-rw-r--r--drivers/iio/adc/ti-adc161s626.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/adc/ti-adc161s626.c b/drivers/iio/adc/ti-adc161s626.c
index 75ca7f1c8726..b789891dcf49 100644
--- a/drivers/iio/adc/ti-adc161s626.c
+++ b/drivers/iio/adc/ti-adc161s626.c
@@ -71,7 +71,7 @@ struct ti_adc_data {
u8 read_size;
u8 shift;
- u8 buffer[16] ____cacheline_aligned;
+ u8 buffer[16] __aligned(IIO_DMA_MINALIGN);
};
static int ti_adc_read_measurement(struct ti_adc_data *data,