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| author | Ingo Molnar <mingo@elte.hu> | 2010-03-09 19:11:53 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-03-09 19:11:53 +0300 |
| commit | 548b84166917d6f5e2296123b85ad24aecd3801d (patch) | |
| tree | 0ab0300e23a02df0fe3c0579627e4998bb122c00 /drivers/ide/ide-timings.c | |
| parent | cfb581bcd4f8c158c6f2b48bf5e232bb9e6855c0 (diff) | |
| parent | 57d54889cd00db2752994b389ba714138652e60c (diff) | |
| download | linux-548b84166917d6f5e2296123b85ad24aecd3801d.tar.xz | |
Merge commit 'v2.6.34-rc1' into perf/urgent
Conflicts:
tools/perf/util/probe-event.c
Merge reason: Pick up -rc1 and resolve the conflict as well.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'drivers/ide/ide-timings.c')
| -rw-r--r-- | drivers/ide/ide-timings.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c index 001a56365be5..0e05f75934c9 100644 --- a/drivers/ide/ide-timings.c +++ b/drivers/ide/ide-timings.c @@ -166,12 +166,13 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed, if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */ memset(&p, 0, sizeof(p)); - if (speed <= XFER_PIO_2) - p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; - else if ((speed <= XFER_PIO_4) || - (speed == XFER_PIO_5 && !ata_id_is_cfa(id))) - p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; - else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) + if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) { + if (speed <= XFER_PIO_2) + p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; + else if ((speed <= XFER_PIO_4) || + (speed == XFER_PIO_5 && !ata_id_is_cfa(id))) + p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; + } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) p.cycle = id[ATA_ID_EIDE_DMA_MIN]; ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); @@ -185,11 +186,10 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed, /* * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, * S.M.A.R.T and some other commands. We have to ensure that the - * DMA cycle timing is slower/equal than the fastest PIO timing. + * DMA cycle timing is slower/equal than the current PIO timing. */ if (speed >= XFER_SW_DMA_0) { - u8 pio = ide_get_best_pio_mode(drive, 255, 5); - ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT); + ide_timing_compute(drive, drive->pio_mode, &p, T, UT); ide_timing_merge(&p, t, t, IDE_TIMING_ALL); } |