diff options
| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2023-09-21 08:57:03 +0300 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2023-09-26 00:35:14 +0300 |
| commit | 3521fa63c1ee7414e6ba0fdf98b82b07939147d9 (patch) | |
| tree | 003525bf3b124c75a8ae1a66a39dd5daa91763ca /drivers/i3c | |
| parent | 4c36f656b7d1fc00643730c5845c19b3e15be856 (diff) | |
| download | linux-3521fa63c1ee7414e6ba0fdf98b82b07939147d9.tar.xz | |
i3c: mipi-i3c-hci: Resume controller explicitly
On an HW I'm using in enabling work the RESUME bit is not set in the
HC_CONTROLLER register when Host Controller goes to halt state. Value 1
should mean controller is suspended when reading and writing 1 resumes it.
Because of this erratic behaviour plain HC_CONTROL read and write back
won't resume the controller. Therefore do it by setting the RESUME bit
explicitly.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/r/20230921055704.1087277-12-jarkko.nikula@linux.intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'drivers/i3c')
| -rw-r--r-- | drivers/i3c/master/mipi-i3c-hci/core.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index d7fe8e62820a..1ae56a5699c6 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -174,8 +174,7 @@ static void i3c_hci_bus_cleanup(struct i3c_master_controller *m) void mipi_i3c_hci_resume(struct i3c_hci *hci) { - /* the HC_CONTROL_RESUME bit is R/W1C so just read and write back */ - reg_write(HC_CONTROL, reg_read(HC_CONTROL)); + reg_set(HC_CONTROL, HC_CONTROL_RESUME); } /* located here rather than pio.c because needed bits are in core reg space */ |