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| author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2018-08-31 18:11:12 +0300 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2018-09-03 00:51:15 +0300 |
| commit | 1bb39959623b438d6b7705abfd0538e8ef4f5f0f (patch) | |
| tree | 0baa02df2f094bec970ed00bbbb2f3725d5a14d5 /drivers/i2c/busses/i2c-designware-core.h | |
| parent | ffbc01bff2ef98430e4ab486b878f04fe7bb7c29 (diff) | |
| download | linux-1bb39959623b438d6b7705abfd0538e8ef4f5f0f.tar.xz | |
i2c: designware: add MSCC Ocelot support
The Microsemi Ocelot I2C controller is a designware IP. It also has a
second set of registers to allow tweaking SDA hold time and spike
filtering.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[wsa: made one function static]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses/i2c-designware-core.h')
| -rw-r--r-- | drivers/i2c/busses/i2c-designware-core.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index f6cad20a86ff..5b550ab9a009 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -225,6 +225,7 @@ struct dw_i2c_dev { struct device *dev; void __iomem *base; + void __iomem *ext; struct completion cmd_complete; struct clk *clk; struct reset_control *rst; @@ -279,6 +280,8 @@ struct dw_i2c_dev { #define ACCESS_INTR_MASK 0x00000004 #define MODEL_CHERRYTRAIL 0x00000100 +#define MODEL_MSCC_OCELOT 0x00000200 +#define MODEL_MASK 0x00000f00 u32 dw_readl(struct dw_i2c_dev *dev, int offset); void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset); |