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authorMugunthan V N <mugunthanvnm@ti.com>2013-06-18 13:34:35 +0400
committerDavid S. Miller <davem@davemloft.net>2013-06-20 05:33:58 +0400
commit6d3d76f877ca061911343d5d1650458906fdf0ea (patch)
tree769a950b177667066eee283deda5b40bfcf8218f /drivers/hwmon/mcp3021.c
parent2bd470fc08cbbfd4f2e53a620362806620d217ed (diff)
downloadlinux-6d3d76f877ca061911343d5d1650458906fdf0ea.tar.xz
drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume
Due to some hardware integration issue, CPSW sliver modules requires a reset across suspend/resume cycle for a successful clock gating to CPGMAC (CPSW and Davinci MDIO) in AM335x PG1.0. This issue is fixed in PG2.x, though to support suspend/resume on PG1.0 this reset is required. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/hwmon/mcp3021.c')
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