diff options
| author | Christian König <deathsimple@vodafone.de> | 2012-03-07 14:28:57 +0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2012-03-07 18:07:29 +0400 |
| commit | 0be70439f2dcf4a2048e4b02f23f2c239b35a110 (patch) | |
| tree | df0e58ec744a8dfd76b143cfbbb8db7691cb2158 /drivers/gpu | |
| parent | dac12d1f5ef228e132c2457dc214e0703533b016 (diff) | |
| download | linux-0be70439f2dcf4a2048e4b02f23f2c239b35a110.tar.xz | |
drm/radeon: fix a semaphore deadlock on pre cayman asics
The out of order execution of semaphore commands on
pre cayman asics doesn't work correctly and can
cause deadlocks, so turn it off for now.
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index fbcd84803b60..17ca72ce3027 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2362,6 +2362,9 @@ void r600_semaphore_ring_emit(struct radeon_device *rdev, uint64_t addr = semaphore->gpu_addr; unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; + if (rdev->family < CHIP_CAYMAN) + sel |= PACKET3_SEM_WAIT_ON_SIGNAL; + radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); radeon_ring_write(ring, addr & 0xffffffff); radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 3ee1fd7ef394..9b23670716f1 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h @@ -831,6 +831,7 @@ #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 #define PACKET3_INDIRECT_BUFFER_MP 0x38 #define PACKET3_MEM_SEMAPHORE 0x39 +# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) # define PACKET3_SEM_SEL_WAIT (0x7 << 29) #define PACKET3_MPEG_INDEX 0x3A |