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| author | Tom St Denis <tom.stdenis@amd.com> | 2023-08-24 16:23:04 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-02 23:18:11 +0300 |
| commit | 60917ce8f88980ed26ddeb7577ae3bcc0e30311c (patch) | |
| tree | 384ee72e3a0cb156685c760050ba11f05657c2c4 /drivers/gpu | |
| parent | 53efeba35d71db3ef5fd4c483748945c1e765adc (diff) | |
| download | linux-60917ce8f88980ed26ddeb7577ae3bcc0e30311c.tar.xz | |
drm/amd/amdgpu: update GFX12 wave data registers
Update the registers for gfx12.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 68a66ccb0100..730d57a10077 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -659,8 +659,8 @@ static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, * zero here */ WARN_ON(simd != 0); - /* type 3 wave data */ - dst[(*no_fields)++] = 3; + /* type 4 wave data */ + dst[(*no_fields)++] = 4; dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); @@ -675,6 +675,15 @@ static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); } static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, |