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| author | Alexandre Courbot <acourbot@nvidia.com> | 2016-02-26 12:06:52 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-03-04 18:24:56 +0300 |
| commit | 097452e61366a939a4772332181cea7cdcc74760 (patch) | |
| tree | ba2f85ae6a48c6930b51e8cef4c2a691bb4f788a /drivers/gpu/host1x/dev.h | |
| parent | 92e963f50fc74041b5e9e744c330dca48e04f08d (diff) | |
| download | linux-097452e61366a939a4772332181cea7cdcc74760.tar.xz | |
gpu: host1x: Set DMA mask
The default DMA mask covers a 32 bits address range, but host1x devices
can address a larger range on TK1 and TX1. Set the DMA mask to the range
addressable when we use the IOMMU to prevent the use of bounce buffers.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/host1x/dev.h')
| -rw-r--r-- | drivers/gpu/host1x/dev.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h index 0b6e8e9629c5..dace124994bb 100644 --- a/drivers/gpu/host1x/dev.h +++ b/drivers/gpu/host1x/dev.h @@ -96,6 +96,7 @@ struct host1x_info { int nb_mlocks; /* host1x: number of mlocks */ int (*init)(struct host1x *); /* initialize per SoC ops */ int sync_offset; + u64 dma_mask; /* mask of addressable memory */ }; struct host1x { |