diff options
| author | Wenjing Liu <wenjing.liu@amd.com> | 2024-06-17 19:58:35 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-07-01 23:10:35 +0300 |
| commit | b6d508533fa1371d870628a88b74c831c5881cde (patch) | |
| tree | ae97c87de9a7ad68c888f65a6842bb5cded2a696 /drivers/gpu/drm | |
| parent | d6d884b68ad65c832be5ba22ac61dc7173059d9a (diff) | |
| download | linux-b6d508533fa1371d870628a88b74c831c5881cde.tar.xz | |
drm/amd/display: fix a crash when clock source is reference for non otg master pipe
[why]
The function enumerates all pipes without checking pipe type. It is only
supposed to call program pixel clock for OTG master pipe only.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 606b2411eee9..45fe17a46890 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -306,27 +306,29 @@ static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr struct dc_state *context, int ref_dtbclk_khz) { - struct dccg *dccg = clk_mgr->dccg; - uint32_t tg_mask = 0; int i; + struct dccg *dccg = clk_mgr->dccg; + struct pipe_ctx *otg_master; + bool use_hpo_encoder; - for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - /* use mask to program DTO once per tg */ - if (pipe_ctx->stream_res.tg && - !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { - tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); - - if (dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { - pipe_ctx->clock_source->funcs->program_pix_clk( - pipe_ctx->clock_source, - &pipe_ctx->stream_res.pix_clk_params, - dccg->ctx->dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), - &pipe_ctx->pll_settings); - } - } + for (i = 0; i < context->stream_count; i++) { + otg_master = resource_get_otg_master_for_stream( + &context->res_ctx, context->streams[i]); + ASSERT(otg_master); + ASSERT(otg_master->clock_source); + ASSERT(otg_master->clock_source->funcs->program_pix_clk); + ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0); + + use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master); + if (!use_hpo_encoder) + continue; + + otg_master->clock_source->funcs->program_pix_clk( + otg_master->clock_source, + &otg_master->stream_res.pix_clk_params, + dccg->ctx->dc->link_srv->dp_get_encoding_format(&otg_master->link_config.dp_link_settings), + &otg_master->pll_settings); } } |