diff options
| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2017-11-24 20:13:31 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2017-11-24 20:20:04 +0300 |
| commit | 3452fa3095e91acbcb1f6290e0d70fa7d3695a3a (patch) | |
| tree | f08389181106f248f2093cc4acea0b2016c75a1d /drivers/gpu/drm | |
| parent | a54b1873c0e3ffec3041cf72cb10d986d6bc4fe5 (diff) | |
| download | linux-3452fa3095e91acbcb1f6290e0d70fa7d3695a3a.tar.xz | |
drm/i915/pmu: Aggregate all RC6 states into one counter
Chris has discovered that RC6, RC6p and RC6pp counters are mutually
exclusive, and even that on some SNB SKUs you get RC6p increasing, and on
the others RC6.
Furthermore RC6p and RC6pp were only present starting from GEN6 until,
GEN7, not including Haswell.
All this combined makes it questionable whether we need to reserve new ABI
for these counters. One idea was to just combine them all under the RC6
counter to simplify things for userspace. So that is what this patch does.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171124171331.17981-1-tvrtko.ursulin@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pmu.c | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 39310cf13c3a..3357b690ce90 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -359,11 +359,6 @@ static int i915_pmu_event_init(struct perf_event *event) if (!HAS_RC6(i915)) ret = -ENODEV; break; - case I915_PMU_RC6p_RESIDENCY: - case I915_PMU_RC6pp_RESIDENCY: - if (!HAS_RC6p(i915)) - ret = -ENODEV; - break; default: ret = -ENOENT; break; @@ -421,16 +416,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event) IS_VALLEYVIEW(i915) ? VLV_GT_RENDER_RC6 : GEN6_GT_GFX_RC6); - intel_runtime_pm_put(i915); - break; - case I915_PMU_RC6p_RESIDENCY: - intel_runtime_pm_get(i915); - val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); - intel_runtime_pm_put(i915); - break; - case I915_PMU_RC6pp_RESIDENCY: - intel_runtime_pm_get(i915); - val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); + if (HAS_RC6p(i915)) { + val += intel_rc6_residency_ns(i915, + GEN6_GT_GFX_RC6p); + val += intel_rc6_residency_ns(i915, + GEN6_GT_GFX_RC6pp); + } intel_runtime_pm_put(i915); break; } @@ -708,8 +699,6 @@ static struct attribute *i915_pmu_events_attrs[] = { I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS), I915_EVENT(rc6-residency, I915_PMU_RC6_RESIDENCY, "ns"), - I915_EVENT(rc6p-residency, I915_PMU_RC6p_RESIDENCY, "ns"), - I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"), NULL, }; |