diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-01-26 02:03:07 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:28:12 +0300 |
| commit | 3747c88428a199620ca626a196781516c6da12e6 (patch) | |
| tree | 6d39a527123c3fc5463d0dbcdb35f45308cc1adf /drivers/gpu/drm/xe/xe_rtp.c | |
| parent | 564d64f83de9759c1faa4a64ee4aed8465281ecb (diff) | |
| download | linux-3747c88428a199620ca626a196781516c6da12e6.tar.xz | |
drm/xe: Rename xe_rtp_regval to xe_rtp_action
It's true that the struct records the register and the value (in form of
2 masks) to restore, but it also records more fields important to
the application of workarounds/tuning, etc. One important part is what
is the macro used to record these fields: SET/CLR/WR/FIELD_SET/etc.
Thinking of the table as a set of rules + actions is more intuitive than
rules + regval.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_rtp.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_rtp.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c index 9e8d0e43c643..d3484b906d4a 100644 --- a/drivers/gpu/drm/xe/xe_rtp.c +++ b/drivers/gpu/drm/xe/xe_rtp.c @@ -91,13 +91,13 @@ static void rtp_add_sr_entry(const struct xe_rtp_entry *entry, u32 mmio_base, struct xe_reg_sr *sr) { - u32 reg = entry->regval.reg + mmio_base; + u32 reg = entry->action.reg + mmio_base; struct xe_reg_sr_entry sr_entry = { - .clr_bits = entry->regval.clr_bits, - .set_bits = entry->regval.set_bits, - .read_mask = entry->regval.read_mask, - .masked_reg = entry->regval.flags & XE_RTP_FLAG_MASKED_REG, - .reg_type = entry->regval.reg_type, + .clr_bits = entry->action.clr_bits, + .set_bits = entry->action.set_bits, + .read_mask = entry->action.read_mask, + .masked_reg = entry->action.flags & XE_RTP_FLAG_MASKED_REG, + .reg_type = entry->action.reg_type, }; xe_reg_sr_add(sr, reg, &sr_entry); @@ -124,7 +124,7 @@ void xe_rtp_process(const struct xe_rtp_entry *entries, struct xe_reg_sr *sr, for (entry = entries; entry && entry->name; entry++) { u32 mmio_base = 0; - if (entry->regval.flags & XE_RTP_FLAG_FOREACH_ENGINE) { + if (entry->action.flags & XE_RTP_FLAG_FOREACH_ENGINE) { struct xe_hw_engine *each_hwe; enum xe_hw_engine_id id; @@ -135,7 +135,7 @@ void xe_rtp_process(const struct xe_rtp_entry *entries, struct xe_reg_sr *sr, rtp_add_sr_entry(entry, gt, mmio_base, sr); } } else if (rule_matches(gt, hwe, entry)) { - if (entry->regval.flags & XE_RTP_FLAG_ENGINE_BASE) + if (entry->action.flags & XE_RTP_FLAG_ENGINE_BASE) mmio_base = hwe->mmio_base; rtp_add_sr_entry(entry, gt, mmio_base, sr); |