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| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2017-02-24 17:19:59 +0300 |
|---|---|---|
| committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2017-02-27 10:09:14 +0300 |
| commit | 62b695662a2413286a25df418b0af665bf2899c5 (patch) | |
| tree | f64228eb65287bb130d31e85ea6f5b9ecb067cc6 /drivers/gpu/drm/vc4 | |
| parent | 71cc22e5db8994ff69c947a296235e8547039188 (diff) | |
| download | linux-62b695662a2413286a25df418b0af665bf2899c5.tar.xz | |
drm/i915: Only enable DDI IO power domains after enabling DPLL
According to bspec, the DDI IO power domains should be enabled after
enabling the DPLL and mapping it to the DDI. The current order doesn't
seem to create problems with Skylake and Kabylake, but causes enable
timeouts in Geminilake.
v2: Rebase.
- Take power domain references before sanitizing encoders. (Imre)
- Add comment to get_encoder_power_domains() defition. (Ander)
v3: Don't put the domain if called with HSW/BDW's analog encoder. (CI)
v4: Put IO power domain before unmapping DPLL. (Imre)
- Change return type of intel_ddi_get_power_domains() to u64. (Imre)
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> # v1
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170224141959.5955-1-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/vc4')
0 files changed, 0 insertions, 0 deletions