diff options
| author | Dave Airlie <airlied@redhat.com> | 2016-03-14 02:48:04 +0300 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2016-03-14 02:48:04 +0300 |
| commit | 67d1c0a25c05e2105d12abd9c0172d2d5c0e7654 (patch) | |
| tree | ec5478f2b8e7510656a9b64d1b607a53014f1c33 /drivers/gpu/drm/vc4/vc4_regs.h | |
| parent | c3d7a1d1e61e0ae94a89fbd0e2d4ad1eed9499c6 (diff) | |
| parent | 6a609209865247cc748e90158c99f374f79b494c (diff) | |
| download | linux-67d1c0a25c05e2105d12abd9c0172d2d5c0e7654.tar.xz | |
Merge tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux into drm-next
This pull request fixes the major VC4 HDMI modesetting bugs found when
the first wave of users showed up in Raspbian.
* tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux:
drm/vc4: Initialize scaler DISPBKGND on modeset.
drm/vc4: Fix setting of vertical timings in the CRTC.
drm/vc4: Fix the name of the VSYNCD_EVEN register.
drm/vc4: Add another reg to HDMI debug dumping.
drm/vc4: Bring HDMI up from power off if necessary.
drm/vc4: Fix a framebuffer reference leak on async flip interrupt.
Diffstat (limited to 'drivers/gpu/drm/vc4/vc4_regs.h')
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_regs.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index 25df20ef939c..bf42a8e87111 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -187,7 +187,7 @@ # define PV_VCONTROL_CONTINUOUS BIT(1) # define PV_VCONTROL_VIDEN BIT(0) -#define PV_VSYNCD 0x08 +#define PV_VSYNCD_EVEN 0x08 #define PV_HORZA 0x0c # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) @@ -350,6 +350,17 @@ # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 #define SCALER_DISPBKGND0 0x00000044 +# define SCALER_DISPBKGND_AUTOHS BIT(31) +# define SCALER_DISPBKGND_INTERLACE BIT(30) +# define SCALER_DISPBKGND_GAMMA BIT(29) +# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) +# define SCALER_DISPBKGND_TESTMODE_SHIFT 25 +/* Enables filling the scaler line with the RGB value in the low 24 + * bits before compositing. Costs cycles, so should be skipped if + * opaque display planes will cover everything. + */ +# define SCALER_DISPBKGND_FILL BIT(24) + #define SCALER_DISPSTAT0 0x00000048 #define SCALER_DISPBASE0 0x0000004c # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) @@ -362,6 +373,9 @@ # define SCALER_DISPSTATX_EMPTY BIT(28) #define SCALER_DISPCTRL1 0x00000050 #define SCALER_DISPBKGND1 0x00000054 +#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ + (x) * (SCALER_DISPBKGND1 - \ + SCALER_DISPBKGND0)) #define SCALER_DISPSTAT1 0x00000058 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ (x) * (SCALER_DISPSTAT1 - \ @@ -456,6 +470,8 @@ #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 #define VC4_HD_M_CTL 0x00c +# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) +# define VC4_HD_M_RAM_STANDBY (3 << 4) # define VC4_HD_M_SW_RST BIT(2) # define VC4_HD_M_ENABLE BIT(0) |