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authorThierry Reding <treding@nvidia.com>2015-01-28 17:25:54 +0300
committerThierry Reding <treding@nvidia.com>2015-04-02 19:49:22 +0300
commit9d910b6068be9b6670d0ebba2ddc3e7816dd8881 (patch)
tree4f9c9142274eaca99e22b402c8816805f57d61ac /drivers/gpu/drm/tegra
parentd0852ab9bb63aaf8e31d39f8819e67ce210d8dbb (diff)
downloadlinux-9d910b6068be9b6670d0ebba2ddc3e7816dd8881.tar.xz
drm/tegra: dc: Document tegra_dc_state_setup_clock()
This function is called by output drivers so should be documented. While at it, move it to a more appropriate location. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/dc.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 1ec24c37d310..076769aba42e 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1164,6 +1164,18 @@ static int tegra_dc_set_timings(struct tegra_dc *dc,
return 0;
}
+/**
+ * tegra_dc_state_setup_clock - check clock settings and store them in atomic
+ * state
+ * @dc: display controller
+ * @crtc_state: CRTC atomic state
+ * @clk: parent clock for display controller
+ * @pclk: pixel clock
+ * @div: shift clock divider
+ *
+ * Returns:
+ * 0 on success or a negative error-code on failure.
+ */
int tegra_dc_state_setup_clock(struct tegra_dc *dc,
struct drm_crtc_state *crtc_state,
struct clk *clk, unsigned long pclk,