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| author | Thierry Reding <treding@nvidia.com> | 2014-12-08 18:32:47 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-01-27 12:14:58 +0300 |
| commit | 666cb873328b5075eb511662858bab02d084ff64 (patch) | |
| tree | 022b213d4e97a05efe37b1b5dcef1e0656a972e7 /drivers/gpu/drm/tegra/hdmi.c | |
| parent | 8f604f8c4dd2d5383f567856450ba12764061c12 (diff) | |
| download | linux-666cb873328b5075eb511662858bab02d084ff64.tar.xz | |
drm/tegra: dc: Unify enabling the display controller
Previously output drivers would enable continuous display mode and power
up the display controller at various points during the initialization.
This is suboptimal because it accesses display controller registers in
output drivers and duplicates a bit of code.
Move this code into the display controller driver and enable the display
controller as the final step of the ->mode_set_nofb() implementation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/hdmi.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 07771956cc94..7e06657ae58b 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -1022,16 +1022,6 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, value |= HDMI_ENABLE; tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); - value &= ~DISP_CTRL_MODE_MASK; - value |= DISP_CTRL_MODE_C_DISPLAY; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); - - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); - value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | - PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); - tegra_dc_commit(dc); /* TODO: add HDCP support */ |