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| author | Thierry Reding <treding@nvidia.com> | 2015-07-07 21:52:07 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 13:18:45 +0300 |
| commit | db199502fa8b62afddde5379d94cac0439202111 (patch) | |
| tree | 521dc19609846d80d89d81193fb5fc16d5cab368 /drivers/gpu/drm/tegra/dp.h | |
| parent | cb072eebfa038361b4f578b65a205ad0abc6fe88 (diff) | |
| download | linux-db199502fa8b62afddde5379d94cac0439202111.tar.xz | |
drm/tegra: dp: Read TPS3 capability from sink
The TPS3 capability can be exposed by DP 1.2 and later sinks if they
support the alternative training pattern for channel equalization.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dp.h')
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index d6ae477bab5c..999078812943 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -23,6 +23,13 @@ struct drm_dp_link_caps { bool enhanced_framing; /** + * tps3_supported: + * + * training pattern sequence 3 supported for equalization + */ + bool tps3_supported; + + /** * @fast_training: * * AUX CH handshake not required for link training |