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| author | Alex Deucher <alexdeucher@gmail.com> | 2011-05-20 12:34:17 +0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-05-20 14:02:22 +0400 |
| commit | 86a94defe2b88380c28547d7053633b26a397d42 (patch) | |
| tree | 5f18745f77235b364f85c8b74804957b285cca4e /drivers/gpu/drm/savage | |
| parent | 8e8e523d865490e95ed7c9d2e173c02648d6be90 (diff) | |
| download | linux-86a94defe2b88380c28547d7053633b26a397d42.tar.xz | |
drm/radeon/kms: fix up DP clock programming on DCE4/5
In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
depending on the asic. The crtc virtual pixel clock is derived from
the DP ref clock.
- DCE4: PPLL or ext clock
- DCE5: DCPLL or ext clock
Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
PPLL/DCPLL programming and only program the DP DTO for the
crtc virtual pixel clock.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/savage')
0 files changed, 0 insertions, 0 deletions