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| author | Urja Rannikko <urjaman@gmail.com> | 2019-03-18 18:44:12 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2019-03-31 01:39:12 +0300 |
| commit | a5c0fa44e9c18223a6651f2697e97b223a693c3a (patch) | |
| tree | 1dfbeba8fe4ebd59f66cb50e3d6ca52d917d4c62 /drivers/gpu/drm/rockchip/rockchip_drm_vop.c | |
| parent | 530b28426a94b822b3c03491cde5c9a961d80e7f (diff) | |
| download | linux-a5c0fa44e9c18223a6651f2697e97b223a693c3a.tar.xz | |
drm/rockchip: vop: Support dithering to RGB666
Splits out the dither register bits and introduces
the same config enumerations as in the rockchip kernel tree.
Tested to fix the banding on my ASUS C201.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20190318154412.26994-1-urjaman@gmail.com
Diffstat (limited to 'drivers/gpu/drm/rockchip/rockchip_drm_vop.c')
| -rw-r--r-- | drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index c7d4c6073ea5..a7cbf6c9a153 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1029,6 +1029,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; + int dither_bpc = s->output_bpc ? s->output_bpc : 10; int ret; mutex_lock(&vop->vop_lock); @@ -1086,11 +1087,19 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; - if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8) + if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else VOP_REG_SET(vop, common, pre_dither_down, 0); + if (dither_bpc == 6) { + VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); + VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); + VOP_REG_SET(vop, common, dither_down_en, 1); + } else { + VOP_REG_SET(vop, common, dither_down_en, 0); + } + VOP_REG_SET(vop, common, out_mode, s->output_mode); VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); |