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author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2015-09-22 22:15:54 +0300 |
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committer | Jani Nikula <jani.nikula@intel.com> | 2015-09-23 10:13:50 +0300 |
commit | 41b578fb0e8b930f2470d3f673b0fa279e77a7b8 (patch) | |
tree | 5dbeea2d098f6927701823083543fd589d44a100 /drivers/gpu/drm/radeon/uvd_v4_2.c | |
parent | 95d0be61286bcc3fc987043fe3a9553adca02919 (diff) | |
download | linux-41b578fb0e8b930f2470d3f673b0fa279e77a7b8.tar.xz |
drm/i915: workaround bad DSL readout v3
On HSW at least (still testing other platforms, but should be harmless
elsewhere), the DSL reg reads back as 0 when read around vblank start
time. This ends up confusing the atomic start/end checking code, since
it causes the update to appear as if it crossed a frame count boundary.
Avoid the problem by making sure we don't return scanline_offset from
the get_crtc_scanline function. In moving the code there, I add to add
an additional delay since it could be called and have a legitimate 0
result for some time (depending on the pixel clock).
v2: move hsw dsl read hack to get_crtc_scanline (Ville)
v3: use break instead of goto (Ville)
update comment with workaround details (Ville)
References: https://bugs.freedesktop.org/show_bug.cgi?id=91579
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/uvd_v4_2.c')
0 files changed, 0 insertions, 0 deletions