diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2012-12-06 00:59:11 +0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-28 03:15:48 +0400 |
| commit | 06793dfba2215f3d31a7a12e5fd8901f18ee035a (patch) | |
| tree | bfbfc972134cf100e1bc93fda7092c1f6664463c /drivers/gpu/drm/radeon/sumo_dpm.c | |
| parent | f85392bcf94c5ae8bf55852827dcfa46f86502dc (diff) | |
| download | linux-06793dfba2215f3d31a7a12e5fd8901f18ee035a.tar.xz | |
drm/radeon: add dpm UVD handling for sumo asics
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/sumo_dpm.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/sumo_dpm.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index 69792e4ac1ce..7bd3fca175de 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -811,6 +811,40 @@ static void sumo_program_bootup_state(struct radeon_device *rdev) sumo_power_level_enable(rdev, i, false); } +static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev) +{ + struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); + struct sumo_ps *current_ps = sumo_get_ps(rdev->pm.dpm.current_ps); + + if ((rdev->pm.dpm.requested_ps->vclk == rdev->pm.dpm.current_ps->vclk) && + (rdev->pm.dpm.requested_ps->dclk == rdev->pm.dpm.current_ps->dclk)) + return; + + if (new_ps->levels[new_ps->num_levels - 1].sclk >= + current_ps->levels[current_ps->num_levels - 1].sclk) + return; + + radeon_set_uvd_clocks(rdev, rdev->pm.dpm.requested_ps->vclk, + rdev->pm.dpm.requested_ps->dclk); +} + +static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev) +{ + struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps); + struct sumo_ps *current_ps = sumo_get_ps(rdev->pm.dpm.current_ps); + + if ((rdev->pm.dpm.requested_ps->vclk == rdev->pm.dpm.current_ps->vclk) && + (rdev->pm.dpm.requested_ps->dclk == rdev->pm.dpm.current_ps->dclk)) + return; + + if (new_ps->levels[new_ps->num_levels - 1].sclk < + current_ps->levels[current_ps->num_levels - 1].sclk) + return; + + radeon_set_uvd_clocks(rdev, rdev->pm.dpm.requested_ps->vclk, + rdev->pm.dpm.requested_ps->dclk); +} + void sumo_take_smu_control(struct radeon_device *rdev, bool enable) { /* This bit selects who handles display phy powergating. @@ -1096,6 +1130,22 @@ static void sumo_cleanup_asic(struct radeon_device *rdev) sumo_take_smu_control(rdev, false); } +static void sumo_uvd_init(struct radeon_device *rdev) +{ + u32 tmp; + + tmp = RREG32(CG_VCLK_CNTL); + tmp &= ~VCLK_DIR_CNTL_EN; + WREG32(CG_VCLK_CNTL, tmp); + + tmp = RREG32(CG_DCLK_CNTL); + tmp &= ~DCLK_DIR_CNTL_EN; + WREG32(CG_DCLK_CNTL, tmp); + + /* 100 Mhz */ + radeon_set_uvd_clocks(rdev, 10000, 10000); +} + static int sumo_set_thermal_temperature_range(struct radeon_device *rdev, int min_temp, int max_temp) { @@ -1188,6 +1238,8 @@ int sumo_dpm_set_power_state(struct radeon_device *rdev) if (pi->enable_dynamic_patch_ps) sumo_apply_state_adjust_rules(rdev); + if (pi->enable_dpm) + sumo_set_uvd_clock_before_set_eng_clock(rdev); sumo_update_current_power_levels(rdev); if (pi->enable_boost) { sumo_enable_boost(rdev, false); @@ -1211,6 +1263,8 @@ int sumo_dpm_set_power_state(struct radeon_device *rdev) } if (pi->enable_boost) sumo_enable_boost(rdev, true); + if (pi->enable_dpm) + sumo_set_uvd_clock_after_set_eng_clock(rdev); return 0; } @@ -1237,6 +1291,7 @@ void sumo_dpm_setup_asic(struct radeon_device *rdev) sumo_program_acpi_power_level(rdev); sumo_enable_acpi_pm(rdev); sumo_take_smu_control(rdev, true); + sumo_uvd_init(rdev); } void sumo_dpm_display_configuration_changed(struct radeon_device *rdev) |