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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-23 17:41:05 +0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-08-31 00:30:08 +0400 |
| commit | 22c775ce80ed921fe9490f3cc2ca66dcda44f572 (patch) | |
| tree | 5c330689c876b94c34857feefdac1b2cbb27cbc3 /drivers/gpu/drm/radeon/si.c | |
| parent | 1fd11777c2f0e6b6b37432b984bf40e3c6072f23 (diff) | |
| download | linux-22c775ce80ed921fe9490f3cc2ca66dcda44f572.tar.xz | |
drm/radeon: implement clock and power gating for CIK (v3)
Only the APUs support power gating.
v2: disable cgcg for now
v3: workaround hw issue in mgcg
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/si.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 8b8963d4a732..4f91e1f4d814 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -4901,7 +4901,7 @@ static void si_set_uvd_dcm(struct radeon_device *rdev, WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2); } -static void si_init_uvd_internal_cg(struct radeon_device *rdev) +void si_init_uvd_internal_cg(struct radeon_device *rdev) { bool hw_mode = true; |